The present invention generally relates to the use of a process monitor circuit for critical-path testing for RapidChip® and ASIC devices, and more specifically relates to built-in self test circuitry for use with a process monitor circuit for RapidChip® and ASIC devices.
The existing process monitor circuit for RapidChip® and ASIC devices utilizes a gated ring oscillator to drive a counter. By gating the oscillator for a known period of time, the resultant 10-bit value of the counter provides an indication of the speed of the ring oscillator. This 10-bit value is then shifted off-chip through a device output pin for analysis by the tester to determine whether the device falls within the manufacturing process window. Since the 10-bit value which is generated is non-deterministic, meaning it can have a wide range of acceptable values, this approach requires that the automated test equipment (ATE) capture the serial data from the device-under-test (DUT) and convert it to a number which can then be tested for a pass/fail condition. In cases where the 10-bit value must be retained for further use in the manufacturing test flow, this approach is the only method that will work. However, in a situation where the 10-bit value need only be tested to pass/fail limits, the aforementioned approach is not ideal in that a typical ATE is not designed to test digital words per se.
The disadvantage of the existing solution is that the tester platforms capable of digital capture are very limited, both in system availability and with respect to the tester pin count of such a tester.